1. Field of the Invention
Generally, the present disclosure relates to the manufacture of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using strain-inducing sources, such as stressed shallow trench isolation (STI) trenches, to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced for manufacturing complex integrated circuits, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. The continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques. For example, to compensate for short channel effects, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length. This techniques offers the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile and/or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, compressive strain along the channel length direction in the channel region of a silicon layer having a standard crystallographic orientation may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. On the other hand, the creation of tensile strain along the channel length direction in the channel region of an N-channel transistor may increase electron mobility. The introduction of stress or strain engineering into the process of integrated circuit fabrication is an extremely promising approach for further device generations since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Therefore, in some approaches, the hole mobility of PMOS transistors is enhanced by forming a strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create strain in the adjacent silicon channel region. Similarly, carbon atoms are introduced into the silicon lattice in order to form a lattice having tensile strain in the drain and source regions, thereby achieving a performance gain for N-channel transistors. In this scenario, however, the performance gain may be less than expected due to a variety of issues associated with the formation of a strained silicon carbon material. Further device scaling may involve further performance reducing mechanisms for countering short channel effects, such as increased dopant levels in the channel region, high-k dielectrics in the gate insulation layer and the like. It is, however, of high importance to provide efficient techniques for compensating or over-compensating for such mobility degrading approaches by efficiently increasing the charge carrier mobility for N-channel and P-channel transistors by providing additional efficient strain-inducing mechanisms, which may be used alone or in combination with the above-identified strategies. For example, stressed layers, such as a stressed contact etch stop layer, used for controlling the etch process for forming contact openings in an interlayer dielectric material enclosing the respective transistors, may be formed with a high amount of internal stress that may induce a corresponding strain in the channel regions.
Furthermore, in sophisticated semiconductor devices, isolation trenches are typically used for isolating individual transistors or groups of transistors, wherein silicon dioxide is usually used as an insulating fill material, which typically results in a compressively stressed trench configuration. Thus, the stressed isolation trench may also be used as a strain-inducing source for specific transistor configurations, in which the compressive stress of the isolation trenches is advantageous. However, the conventional process techniques for forming isolation trenches may not provide the required flexibility for addressing the different needs of P-channel transistors and N-channel transistors. Furthermore, the efficiency of the strain-inducing mechanism based on conventional STI techniques may be significantly less compared to other sources, such as stressed contact etch stop layers. Therefore, conventional STI techniques may not provide a significant performance gain, although, in principle, the trench isolations may represent appropriate device locations for endowing a desired type of biaxial strain in the adjacent active semiconductor regions.
The present disclosure is directed to various devices and methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.